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Introduction to Physical Memory Protection (PMP) in RISC-V

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Published 6/2024
Created by Benix Samuel Vincent Theogaraj
MP4 | Video: h264, 1280×720 | Audio: AAC, 44.1 KHz, 2 Ch
Genre: eLearning | Language: English | Duration: 14 Lectures ( 1h 32m ) | Size: 730 MB

Embedded processor memory protection

What you’ll learn:
What is the need for physical memory protection?
What are machine memory protection CSRs and its reset value?
What are the different address matching modes supported?
How to lock and control memory access with PMP?

Requirements:
Basic understanding of RISC-V architecture and microcontrollers

Description:
This course builds from the basics needed to learn about Physical Memory Protection (PMP) Unit and then discusses all the aspects of configuring the PMP in RISC-V and touches on the Control & Status Registers (CSRs) related to PMP. Finally, a sample PMP configuration is discussed to validate the learning. First section introduces the building blocks of a processor, physical memory address,  virtual memory address and memory hierarchy in the light of physical memory protection unit.Second section discusses the need for PMP unit in processor along with the categories of users and memory region attributes.  After the basics on first and second section, third section discusses the RISC-V’s privileged specification rules or constraints for PMP to be compliant. This also discusses the PMP configuration and PMP address CSRs and its layout. Fourth section is the crux which discusses memory addressing modes, memory region encoding and mostly importantly illustrates with a sample PMP configuration from E31 RISC-V processor. This discusses in elaborate the Top of Range(TOR)  and (NAPOT) Naturally aligned power of 2 memory region configuration along with encoding the memory region size. Fifth section on assembly code to configure PMP and see what happens if user access violates the permission set in PMP is yet to be added and in progress.


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