Cadence Design Systems, Inc. , the leader in global electronic design innovation, has unveiled INNOVUS 19.11.000 (ISR1) is part of the broader Cadence digital and signoff suite, which provides customers with an integrated full flow, delivering a predictable path to design closure and also supports Cadence’s Intelligent System Design strategy, accelerating SoC design excellence.
Release 19.11 Overview
New Text Commands and Global Variables
The following table lists the commands that were added to the Innovus software in this release. The second column identifies the corresponding chapter of the Innovus Text Command Reference where the command is documented.
New Command Parameters
The following table lists the parameters that were added to the Innovus software in this release. The second column identifies the corresponding chapter of the Innovus Text Command Reference where the command is documented.
Obsolete Command Parameters
Supported in this Release
The following obsolete text command parameters will continue to be supported in this release, but will be removed in the next major release of the software. Update your scripts to avoid warnings and to ensure compatibility with future releases.
Use the write_lef_abstract command instead.
Removed from Software
The following obsolete text command parameters have been removed from the software.
This parameter has not been replaced.
The Cadence Innovus Implementation System is optimized for the most challenging designs, as well as the latest FinFET 16nm, 14nm, 7nm, and 5nm processes, helping you get an earlier design start with a faster ramp-up. With unique new capabilities in placement, optimization, routing, and clocking, the Innovus system features an architecture that accounts for upstream and downstream steps and effects in the design flow. This architecture minimizes design iterations and provides the runtime boost you’ll need to get to market faster. Using the Innovus system, you’ll be equipped to build integrated, differentiated systems with less risk.
The Innovus system features a variety of key capabilities. Its massively parallel architecture can handle large designs and take advantage of multi-threading on multi-core workstations, as well as distributed processing over networks of computers.
Based on the well-established NanoRoute engine, next-generation slack and power-driven routing with track-aware timing optimization addresses signal integrity early on and improves post-route correlation. The Innovus system includes full-flow multi-objective technology, which makes concurrent electrical and physical optimization possible. It also shares a customizable flow via a common UI and user commands with synthesis and signoff tools. As a result, you can take advantage of robust reporting and visualization, improving your design efficiency and productivity across the whole digital flow.
With block sizes growing in both cell count and complexity, the number of macros that need to be positioned in the floorplan is exploding. The Innovus system offers mixed-macro and standard-cell placement, which enables macro locations to be automatically generated, reducing the time to create an optimal floorplan from days to hours.
The latest advances in machine learning computer science are very relevant for digital implementation flows. The Innovus system incorporates machine learning technology to deliver the best PPA for the most challenging, high-performance blocks. The designer has complete control over the machine learning training, to ensure it is customized for their specific design requirements.
Cadence’s Genus Synthesis Solution is tightly integrated with the Innovus system, which enables a seamless move from RTL synthesis to implementation. With shared placement and optimization technology from the GigaPlace and GigaOpt engines for Genus physical synthesis, this offers a big benefit for advanced-node design convergence.
As voltage decreases in the latest FinFET process nodes, IR and EM constraints become increasingly important. The Innovus system includes comprehensive power integrity-aware placement, optimization, clock tree, and routing features to ensure IR and EM violations are addressed during implementation without impacting final PPA.
Cadence’s Tempus Timing Signoff Solution, Quantus Extraction Solution, and Voltus IC Power Integrity Solution are integrated with the Innovus system. With this integration, you can accurately model parasitics, timing, signal, and power integrity effects at the early stage of physical implementation, and achieve faster convergence on these electrical metrics, resulting in more efficient design closure.
Complete flow of innovus tool has been demonstrated in this video. Both command line and GUI mode have been covered in the same video. Important input files for this flow has also been discussed and how to create them has been explained.
Cadence enables global electronic design innovation and plays an essential role in the creation of today’s integrated circuits and electronics. Customers use Cadence software, hardware, IP and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers and research facilities around the world to serve the global electronics industry.
Product: Cadence INNOVUS
Version: 19.11.000 (ISR1) **
Supported Architectures: x86
Website Home Page : http://www.cadence.com
Languages Supported: english
System Requirements: RHEL 6.5 (lnx86) *
Size: 3.9 Gb
* This build is based on the 2018 platform support matrix, linux only. From this release onwards RH6.5 is the minimum requirement.