AMIQ DVT Eclipse IDE 是专为 IC 设计和验证工程师打造的强力集成开发环境（基于 Eclipse 框架），旨在显著提高 SystemVerilog、Verilog、VHDL、e、SystemC 和 PSS 等硬件描述语言的编写、调试及理解效率。它以其实时编译、智能代码补全、可视化项目架构（如图形化UML）和快速代码分析能力，成为 ASIC 和 FPGA 开发的顶级工具。
- 高效开发（提升速度）： 提供智能提示（Auto-complete）、快速修复（Quick Fix）和实时语法检查（On-the-fly syntax check），减少编译错误。
- 代码导航与理解： 能够极其快速地理解复杂且庞大的老旧代码库（Legacy Code），支持强大的代码跳转、符号视图和设计结构可视化，极大减少查找定义和引用关系的时间。
- 全面的验证集成： 深入支持 UVM（Universal Verification Methodology），支持高效编译、单步调试，可无缝集成第三方仿真工具。
- 高级功能：
- DVT Debugger Add-On： 支持即时调试。
- Verissimo Linter： 针对 Verilog/SystemVerilog 的静态分析工具。
- Specador： 自动化代码文档生成。
AMIQ DVT Eclipise IDE 2026 (26.1.8) | 4.7 Gb
AMIQ EDA, a pioneer in integrated development environments (IDEs) for hardware design and verification and a provider of platform-independent software tools for efficient code development and analysis, has launched 26.1.3 release of its Design and Verification Tools (DVT) Eclipse IDE.
What’s new in this release – Date: 23 February 2026
e Language
Features
– DVT-22610 AI Assistant: Ability to render WaveDrom Diagrams in chat
– DVT-24648 AI Assistant: New ‘Explain the selected assertion’ predefined blueprint
Enhancements
– DVT-22640 AI Assistant: Label LLM provider error messages to set them apart from AI Assistant error messages
– DVT-24390 AI Assistant: Ability to configure tool access and permissions in the chat
– DVT-24757 Log Viewer: Ability to use hyperlinks in logs which are not set as current for a project
SystemVerilog
Performance
– DVT-24816 Show usages: Speed-up searching for package parameter references when the package is imported in modules with lots of port connections
– DVT-24823 Design Breadcrumb: Speed-up computation time for designs containing many generate blocks
Features
– DVT-22610 AI Assistant: Ability to render WaveDrom Diagrams in chat
– DVT-24648 AI Assistant: New ‘Explain the selected assertion’ predefined blueprint
Enhancements
– DVT-22640 AI Assistant: Label LLM provider error messages to set them apart from AI Assistant error messages
– DVT-23269 FSM Diagrams: Ability to take into account context from outside the module instance where the generation is triggered
– DVT-24390 AI Assistant: Ability to configure tool access and permissions in the chat
– DVT-24457 Elaboration: Add support for disable statement inside function
– DVT-24591 UVM Runtime Elaboration: Use built-in implementation of UVM DPI-C by default
– DVT-24757 Log Viewer: Ability to use hyperlinks in logs which are not set as current for a project
VHDL
Performance
DVT-24823 Design Breadcrumb: Speed-up computation time for designs containing many generate blocks
Features
DVT-22610 AI Assistant: Ability to render WaveDrom Diagrams in chat
DVT-24648 AI Assistant: New ‘Explain the selected assertion’ predefined blueprint
Enhancements
DVT-22640 AI Assistant: Label LLM provider error messages to set them apart from AI Assistant error messages
DVT-23269 FSM Diagrams: Ability to take into account context from outside the module instance where the generation is triggered
DVT-24390 AI Assistant: Ability to configure tool access and permissions in the chat
DVT-24757 Log Viewer: Ability to use hyperlinks in logs which are not set as current for a project
PSS
Features
– DVT-22610 AI Assistant: Ability to render WaveDrom Diagrams in chat
– DVT-24648 AI Assistant: New ‘Explain the selected assertion’ predefined blueprint
Enhancements
– DVT-22640 AI Assistant: Label LLM provider error messages to set them apart from AI Assistant error messages
– DVT-24390 AI Assistant: Ability to configure tool access and permissions in the chat
– DVT-24757 Log Viewer: Ability to use hyperlinks in logs which are not set as current for a project
Design and Verification Tools (DVT) is an integrated development environment (IDE) for the e language, SystemVerilog, Verilog, Verilog-AMS, VHDL, PSS, SLN, SDL, UPF, CPF. It is similar to well-known programming tools like Visual Studio , NetBeans , and IntelliJ.DVT consists of a parser, a smart code editor, an intuitive graphical user interface, and a comprehensive set of features that help with code writing, inspection, navigation, and debugging. DVT provides capabilities that are specific to the hardware design and verification domain, such as design diagrams, signal tracing, power domains visualization, and verification methodology support.
AMIQ EDA provides design and verification engineers with platform-independent software tools that enable them to increase the speed and quality of new code development, simplify debugging and legacy code maintenance, accelerate language and methodology learning, improve testbench reliability, extract automatically accurate documentation, and implement best coding practices. Its solutions, DVT Eclipse IDE, DVT Debugger, Verissimo SystemVerilog Testbench Linter, and Specador Documentation Generator have been adopted worldwide. AMIQ strives to deliver high quality solutions and customer service responsiveness. For more information about AMIQ EDA and its solutions,
Owner: AMIQ EDA
Product: DVT Eclipse IDE
Version: 2026 version 26.1.8 *
Supported Architectures: x64
Website Home Page : http://www.dvteclipse.com
Languages Supported: english
System Requirements: Windows, Linux, macOs **
Size: 4.7 Gb
* Starting from the January 2026 release (26.1.1), the archive names and the root directory within each archive have been updated to follow a clearer and more consistent naming convention.