Cadence Silicon Signoff and Verification (SSV) 25.1 是Cadence推出的主要针对高端芯片设计的签核与验证平台，于2025年夏季发布基础版本。该版本旨在为复杂IC设计提供高效的物理验证和时序分析能力，旨在提高先进制程的收敛速度和准确性。
- 加速设计收敛： 提供增强的物理验证（Physical Verification）和时序分析功能，助力先进封装和制程技术。
- 高可靠性签核： 确保设计从电路到物理布局的最终一致性与可靠性。
- 增强工作流： 专为满足复杂IC设计的容量和速度要求而设计，优化签名验证流程。
Cadence Design Systems, Inc. announced the new Cadence Silicon Signoff and Verification (SSV) 25.1. This solution encapsulates a set of tools that address a series of electrical and physical signoff and verification steps that designers must perform on their design before tapeout.
Silicon signoff and verification (SSV) encapsulates a set of tools that address a series of electrical and physical signoff and verification steps that designers must perform on their design before tapeout. These steps report errors that require iterative and incremental fixes, also called engineering change orders (ECOs), ensuring the design integrity from an electrical and physical standpoint. All of Cadence’s signoff tools or capabilities are integrated in the Virtuoso platform, providing the same capabilities for mixed-signal and custom designs.
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Cadence is a pivotal leader in electronic design and computational expertise, using its Intelligent System Design strategy to turn design concepts into reality. Cadence customers are the world’s most creative and innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications.
Owner: Cadence
Product Name: Silicon Signoff and Verification (SSV)
Version: 25.1 (25.10.000) Base Release
Supported Architectures: x86_64
Website Home Page : http://www.cadence.com
Languages Supported: english
System Requirements: Linux *
Size: 13.6 Gb
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