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Synopsys IC Compiler II vP-2019.03-SP5 Linux

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Synopsys IC Compiler II vP-2019.03-SP1

IC Compiler II (ICC2) 是行业领先的布局布线解决方案,旨在支持FinFET 16nm以下先进工艺,消除前沿设计面临的性能、功耗、面积 (PPA) 和上市时间等紧迫压力。掌握IC Compiler II的 Fusion融合技术是如何集合整个芯片实现后端的工具,实现设计流程的优化。


Synopsys IC Compiler II vP-2019 | 1.3 Gb

Synopsys, Inc., the world leader in semiconductor design software, is pleased to announce the availability of IC Compiler II vP-2019.03-SP1 is a complete netlist-to-GDSII implementation system that includes early design exploration and prototyping, detailed design planning, block implementation, chip assembly and sign-off driven design closure.

IC Compiler II is the industry leading place and route solution that delivers best-in-class quality-of-results (QoR) for next generation designs across all market verticals and process technologies, while enabling unprecedented productivity. IC Compiler II includes innovative for flat and hierarchical design planning, early design exploration, congestion aware placement and optimization, clock tree synthesis, advanced node routing convergence, manufacturing compliance, and signoff closure.

IC Compiler II is specifically architected to address aggressive performance, power, area (PPA), and time-to-market pressures of leading edge designs. Key technologies include a pervasively parallel optimization framework, multi-objective global placement, routing driven placement optimization, full flow Arc based concurrent clock and data optimization, total power optimization, multi-pattern and FinFET aware flow and machine learning (ML) driven optimization for fast and predictive design closure. Advanced Fusion technologies offer signoff IR drop driven optimization, PrimeTime delay calculation within IC Compiler II, exhaustive path based analysis (PBA) and signoff ECO within place and route for unmatched QoR and design convergence.

Jiangtao Meng, Sr. R&D Manager at Synopsys, discusses how IC Compiler II and Fusion Compiler enable intelligent planning and implementation of complex interconnects through innovative Topological Interconnect Planning (TIP) technology to accelerate project schedules while achieving the highest performance designs.
Synopsys, Inc. is the world leader in electronic design automation (EDA) software for semiconductor design. The company delivers technology-leading semiconductor design and verification platforms and IC manufacturing software products to the global electronics market, enabling the development and production of complex systems-on-chips (SoCs). Synopsys also provides intellectual property and design services to simplify the design process and accelerate time-to-market for its customers. Synopsys is headquartered in Mountain View, California and has offices in more than 60 locations throughout North America, Europe, Japan and Asia.

Product: Synopsys IC Compiler II
Version: vP-2019.03
Supported Architectures: x86_64
Website Home Page : http://www.synopsys.com
Languages Supported: english
System Requirements: Linux *
Size: 1.3 Gb


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