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Cadence PEGASUS 20.10.000 – 22.11.000 Linux

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Cadence PEGASUS 20.10.000 - 22.11.000
Pegasus是一款新一代的芯片物理验证工具,可以大幅缩短高性能SoC或CPU的验证时间。
Pegasus验证系统解决方案是全流程Cadence数字设计与签核套件的新成员,可扩展至数百CPU,设计规则检查(DRC, Design Rule Check )性能最高可提升10倍,周转时间较上一代Cadence解决方案由数日降至数小时。

早期客户已将Pegasus验证系统用于存储、高性能运算、云、服务器和移动应用等领域的大型设计。Pegasus解决方案具备多项优势:

• 大规模并行架构:Pegasus解决方案采用大规模并行架构,拥有前所未有的速度和性能,轻松扩展至数百CPU,助力设计师加快流片速度。

• 缩短全芯片物理验证时间:Pegasus解决方案具备千兆级处理能力,可以近线性扩展至最多960个CPU,助客户大幅缩短DRC签核时间。

• 过渡成本低:Pegasus解决方案基于现行代工厂认证工作规则,客户无需耗费大量学习时间既可实现100% 精确验证。

• 灵活的云计算平台:Pegasus解决方案提供原生云支持,搭建灵活、弹性的运算环境,助客户应对激烈竞争,缩短产品上市时间。

• 高效利用CPU资源:无论何种设备配置和物理位置,Pegasus解决方案的异步处理数据流皆可助客户优化CPU占用,提供最大灵活性以运行丰富的硬件,并实现高速DRC签核。

• 原生兼容Cadence数字与定制设计流程:Pegasus验证系统与Virtuoso定制设计平台无缝整合,支持实时DRC签核检查;采用“正确构建”(correct-by-construction)工作流,设计师得以大幅提高布线效率。通过集成Innovus设计实现系统,设计师可以在流程的不同阶段运行Pegasus验证系统并执行各项检查,主要包括:签核DRC和多重曝光分解;执行色彩平衡校验以提升良率;填充时序感知金属以减少时序收敛迭代;工程设计更改(ECO)期间的增量DRC和金属填充以缩短周转时间;以及全芯片DRC。

德州仪器(Texas Instruments)是Cadence Pegasus验证系统的早期客户之一,已经成功将该全新解决方案扩展至540个CPU,大幅缩短全芯片DRC的运行时间。德州仪器此前的DRC解决方案扩展能力有限,难以应对日益紧张的流片进度。较德州仪器此前使用的解决方案,Pegasus验证系统支持原生云处理,可以预测周转时间,实现数量级运行加速,大幅提升设计团队的整体生产力。


Cadence PEGASUS 20.10.000 – 22.11.000 | 28.2 Gb

Cadence Design Systems, Inc. , the leader in global electronic design innovation, has unveiled Cadence PEGASUS 20.10.000 – 22.11.000 is a cloud-ready physical verification signoff solution that enables engineers to deliver advanced-node integrated circuits (ICs) to market faster. The groundbreaking technology delivers up to 10X improved design rule check (DRC) performance on hundreds of CPUs while also reducing turnaround time from days to hours. The Pegasus system’s innovative architecture and native cloud processing provides an elastic and flexible computing environment, which enables customers to complete full-chip signoff DRC on advanced-node designs in a matter of hours, helping designers deliver products to market faster. The Pegasus system seamlessly integrates with the industry-standard Cadence Virtuoso custom/analog platform, the market-leading Cadence Innovus Implementation System, and mixed-signal flows.

Design rule checking (DRC) can be the one of the biggest bottlenecks in getting a chip out the door. The computation power required for a large DRC run can be staggering. In this episode of Chalk Talk, Amelia Dalton chats with Christian Decoin from Cadence Design Systems about the Pegasus Verification System which will let your DRC fly.
Cadence is a pivotal leader in electronic systems design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to complete systems for the most dynamic market applications, including hyperscale computing, 5G communications, automotive, mobile, aerospace, consumer, industrial and healthcare. For eight years in a row, Fortune magazine has named Cadence one of the 100 Best Companies to Work

Product: Cadence PEGASUS
Version: 20.10.000 – 22.11.000 *
Supported Architectures: x86_64
Website Home Page : http://www.cadence.com
Languages Supported: english
System Requirements: Linux **
Size: 28.2 Gb

* included:
Base_PEGASUS20.10.000_lnx86_1of1
Base_PEGASUS20.20.000_lnx86_1of1
Base_PEGASUS20.30.000_lnx86_1of1
Base_PEGASUS20.40.000_lnx86_1of1
Base_PEGASUS21.10.000_lnx86_1of1
Base_PEGASUS21.20.000_lnx86_1of1
Base_PEGASUS21.30.000_lnx86_1of1
Base_PEGASUS22.10.000_lnx86_1of1
Hotfix_PEGASUS20.11.000-Q2_lnx86_1of1
Hotfix_PEGASUS20.11.100-ISR1_lnx86_1of1
Hotfix_PEGASUS20.31.000_lnx86_1of1
Hotfix_PEGASUS21.21.000_lnx86_1of1
Hotfix_PEGASUS21.31.000_lnx86_1of1
Hotfix_PEGASUS22.11.000_lnx86_1of1


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