Cadence Design Systems, Inc. , the leader in global electronic design innovation, has unveiled Cadence Modus DFT Software Solution 19.10.000 – 22.10.000 is a comprehensive next-generation physically aware design-for-test (DFT), automatic test pattern generation (ATPG), and silicon diagnostics tool.
Concerned about your test costs? Reduce your SoC test time by up to 3X with the Cadence Modus DFT Software Solution. Introducing a new patented 2D Elastic Compression architecture, this next-generation tool enables compression ratios beyond 400X without impacting design size or routing. With a complete suite of industry-standard capabilities for memory BIST, logic BIST, test point insertion, and diagnostics, the solution can help you reduce your production test costs and increase silicon profit margins.
Cadence is a pivotal leader in electronic systems design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to complete systems for the most dynamic market applications, including hyperscale computing, 5G communications, automotive, mobile, aerospace, consumer, industrial and healthcare. For eight years in a row, Fortune magazine has named Cadence one of the 100 Best Companies to Work
Product: Cadence Modus DFT Software Solution
Version: 19.10.000 – 22.10.000
Supported Architectures: x86_64
Website Home Page : http://www.cadence.com
Languages Supported: english
System Requirements: Linux *
Size: 15.9 Gb