Published 9/2025
MP4 | Video: h264, 1280×720 | Audio: AAC, 44.1 KHz, 2 Ch
Language: English | Duration: 3h 58m | Size: 1.68 GB
Understand and build an edge detector based on Sobel filter from scratch in VHDL
What you’ll learn
Fundamentals of image processing and edge detection
Fundamentals of digital arithmetic and signed and unsigned manipulation with VHDL
Finite state machines
Best practices for modular, reusable, VHDL design
Architecting a hardware design and implementing in VHDL
Hands-on practical lab
Project automation with Makefile and python scripts
Requirements
Basic notions on digital electronics and VHDL are needed to get the most from this course
Description
As part of the “Learn FPGA Design with VHDL” hands-on series, this module focuses on implementing the Sobel edge-detection filter — a foundational building block for feature extraction, and image processing on FPGAs.In this course, you will:Learn image processing basicsLearn digital arithmetic basicsLearn to use the numeric_std VHDL package to manipulate signed and unsigned numbersUnderstand the Sobel operator mathematically (why does Sobel filter allows to detect edges?)Architect the Sobel filter and the edge detectorTranslate the algorithm into a hardware module in VHDLVisualize results on VGA for tests on FPGA and via memory dumps for simulationAutomate the generation of the filtered image by running a single command via Makefile and python scriptsThis engineering project is fun and will give you lot of skills in different subjects.By the end, you’ll be able to implement a Sobel edge detector in VHDL. Through this process, you will gain knowledge in image processing. You will also get accustomed to finite state machines, arithmetic on signed and unsigned numbers, RAMs and ROMs, multiplexing and hardware design in general. You will also learn to automate your project. Running all your project with one command is fun, you will gain the sight of applying it to your own projects.
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