Mentor Graphics QuestaSim 是业界最优秀的HDL语言仿真器，它提供最友好的调试环境，是唯一的单内核支持VHDL和Verilog混合仿真的仿真器。是作FPGA/ASIC设计的RTL级和门级电路仿真的首选，它采用直接优化的编译技术、Tcl/Tk技术、和单一内核仿真技术，编译仿真速度快，编译的代码与平台无关，便于保护IP核，个性化的图形界面和用户接口，为用户加快调错提供强有力的手段。全面支持VHDL和Verilog语言的IEEE 标准，支持C/C++功能调用和调试
Mentor, a Siemens business, is pleased to announce the availability of QuestaSim 2021.2.1 comprehensive platform for verification complex designs, is the core simulation and debug engine of the Questa Verification Solution; the comprehensive advanced verification platform capable of reducing the risk of validating complex FPGA and SoC designs.
The Questa Verification Solution from Siemens EDA, a part of Siemens Digital Industries Software, continues to evolve in response to the growing complexity of SoC designs. Besides the sheer size of designs, the inclusion of multiple embedded processors and advanced interconnect systems, increasing software content and the configurability required by multi-platform based designs require a functional verification solution that unifies a broad arsenal of verification solutions. The key to verification success is to decompose the problem and use the best solution for each aspect of the system. This places tremendous importance on the verification plan and the ability to collect metrics throughout the process and across all verification tasks to track progress against the plan, allocate and manage resources efficiently, and identify trends as the project progresses against schedule.
Software has become a major component of SoC system functionality, creating new requirements for block-to system verification reuse and the need for system verification and debug. While software testing of SoC integration and basic functionality as well as the verification of low level driver software can be accomplished in simulation, long, complex sequences that exercise system functionality demand acceleration with full debug visibility. To avoid wasting cycles at the system level, it is critical to identify bugs as early as possible in the process. Questa lets you apply CDC verification, formal verification, mixed-signal verification, portable stimulus, and other powerful technologies to maximize the effectiveness of your verification at the block- and subsystem-level so your system-level verification can focus on system-level functionality, including software, without having to worry about lower-level bugs taking away from your productivity. No one wants to compromise product quality. However, time-tomarket pressures dominate SoC projects. To deliver quality within schedule requires improving the time to achieve coverage and quality goals and improving debug productivity.
The solution is composed of several technologies, each powerful on its own. Applied together, along with a comprehensive database and best-in-class verification management tools, these technologies deliver a powerful answer to the spectrum of verification problems.Unified Simulation is built on a best-in-class simulator. The Questa Advanced Simulator achieves industry-leading performance and capacity through very aggressive, global compile and simulation optimization algorithms for SystemVerilog and VHDL. Questa also supports very fast turnaround time flows and effective library management while maintaining high performance with unique capabilities to pre-optimize and reuse, enabling dramatic regression throughput improvements of up to 3X when running a large suite of tests. The Questa Visualizer debug environment provides high performance, high capacity debugging for both Questa and Veloce, enabling the ue of the same debug environment from simulation to emulation and other engines.
Mentor Graphics QuestaSim 2021 lets users test their chips before executing the chips for actual design, manufacturing or implementation. It can perform advanced and efficient evaluation to ensure the tests are precise without adding much steps or efforts. The debugging of the application is pretty seamless and straightforward. Users can access all the tools at fingertips plus it can perform multi-core simulation and parallel testing which results in high performance and quick testing and debugging. It also includes automated tools for more flexibility and ease.
Mentor Graphics is a technology leader in electronic design automation (EDA), providing software and hardware design solutions that enable companies to develop better electronic products faster and more cost-effectively. The company offers innovative products and solutions that help engineers overcome the design challenges they face in the increasingly complex worlds of board and chip design. Mentor Graphics has the broadest industry portfolio of best-in-class products and is the only EDA company with an embedded software solution.
Product: Mentor Graphics QuestaSim
Version: 2021.2.1
Supported Architectures: x64
Website Home Page : http://www.mentor.com
Languages Supported: english
System Requirements: Linux *
Size: 3.8 Gb
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